Modern ultra-HD display panels demand high-mobility thin-film transistors (TFTs) to support high frame rates. Oxide semiconductor-based TFTs support the fabrication of flexible TFT display panels mainly due to low-temperature processing. Moreover, oxide-based TFTs provide transparency in the visible spectrum due to the wide bandgap and promise higher field-effect mobility. For the channel layer of TFT, among the wide-band-gap oxides, ZnO and its composites (IGZO, AZO, ZTO) are mostly used because of their high transparency, nontoxicity, and high electron mobility. However, the nature of the deposited film: polycrystalline or nanocrystalline affects the carrier mobility significantly. Grain boundaries in polycrystalline and nanocrystalline deposited films act like charge scattering centers and reduce mobility. Moreover, Oxide-based TFTs also suffer from threshold voltage shifts due to prolonged gate bias leading to a change in the driving current. This can create a severe reliability issue in an AMOLED display. If the magnitude of the current decreases below a certain level, a pixel may turn into a dark pixel. Therefore, at the circuit level, one needs to use the voltage-programmed pixel driving scheme to make the OLED current independent of the driver TFTs. Our proposed 6 TFT-1C & 5T-2C pixel circuits can compensate wide range of VTH variations. The proposed 6 TFT-1C pixel circuit ensures the maximum percentage error in OLED current is below 1.14 % for a VT shift of 0 V- 2.1 V. Moreover, The OLED current error was found to be below 0.0018% for a ±0.3% strain in the driving TFT. The proposed low-voltage 5T-2C pixel circuit utilizes improved stacked voltage-programmed pixel circuit topology and delivers a low programming time of 8 µs making it suitable for providing a 120 Hz frame rate for HD displays. The error in organic light emitting diode (OLED) current is within 0.4% over the range of data voltage (3.8 V to 6 V) when the substrate is subjected to both compressive and tensile strains of ± 0.3% and within 10% due to threshold voltage variations under electrical stress.
Kavindra Kandpal is a senior member of IEEE and currently working in the ECE dept. of Indian Institute of Information Technology Allahabad (IIITA) as an assistant professor. He completed his Ph.D. program in the EEE department of BITS Pilani, in the area of oxide-based thin-film transistors in 2018. During his Ph.D., he worked closely with CSIR-CEERI Pilani for experimental work related to TFT fabrication. His research interest includes thin-film deposition, characterization, semiconductor devices, and display electronics. Moreover, He is also actively working in CMOS Memory, Analog and Digital VLSI Design, solid-state applications of topological insulators, Thin Film Transistors, and device-to-circuit integrated design with applications ranging from display electronics, biosensors, and photodetectors. He has more than 52 research publications in peer-reviewed journals and international conferences. He is also a recipient of the IEEE Uttar Pradesh Section Young Professional star for April, 2021.
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